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Javier Fileiv
From France 12:14 PM (GMT+02:00)
$90,000/yr

Active 1 hour ago


Member since Sep 2026

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Senior Embedded Software Engineer

Software Engineer
Available for hire
Years of experience
15+ years
Experience level
Staff
Available for
Full-time
Available from
28 Oct 2026

Senior / Staff Embedded Systems Engineer with 15+ years of experience bridging hardware constraints and robust, deterministic software architecture.
Extensive background across the full embedded lifecycle: from low-level bare-metal bring-up and RTOS-based firmware to Linux BSP integration and protocol stack implementation. Proven track record in safety-critical avionics, automotive telematics, and high-precision wireless systems (UWB, RF).

Core Expertise: • Languages: Modern C, C++, Rust (Certified Cénotélie), Python, Assembly • RTOS & Real-Time: Zephyr RTOS, FreeRTOS, Bare-metal, Concurrency & Synchronization • Embedded Linux: BSP integration, Device Drivers (I2C, SPI, UART, Char), Bootlin training (Embedded Linux & Yocto), Rootfs (Yocto, Buildroot) • Hardware & Connectivity: ARM Cortex-M/A, STM32, NXP, UWB (FiRa/IEEE 802.15.4), BLE, CAN bus, Board Bring-up, JTAG/GDB

💼 Open to permanent roles (CDI): Full Remote (France) or On-Site / Hybrid in the Toulouse area.

Employment History

Staff Senior Embedded Engineer at QORVO 2021 - 2026
- Architected Board Support Packages (BSP) and low-level firmware in Assembly, C, and C++, delivering production-grade UWB radar features and ranging topologies (TWR, OWR, DL-TDoA, UL-TDoA) compliant with FiRa, omlox, and MCTT standards. - Engineered Layer 2 MAC protocol features and session management for multi-device RTLS networks, optimizing throughput, latency, and concurrency across up to 10 active devices in dynamic RF environments. - Integrated and optimized real-time operating systems (Zephyr RTOS, FreeRTOS), tailoring Devicetree/Kconfig hardware descriptions, preemption models, and inter-thread synchronization under strict resource constraints. - Collaborated with cross-functional teams to align interface contracts, de-risk bring-up, and cut time-to-market. - Built an end-to-end automated verification framework using Python, pytest, and GoogleTest integrated into CI/CD pipelines, driving rigorous hardware-in-the-loop and unit testing. - Drove deep-dive debugging and power profiling using GDB, J-Link/JTAG, radare2, and the Nordic PPK2 to resolve edge-case regressions and minimize power draw. Tech Stack: Assembly, C/C++, Rust, Python, Zephyr RTOS, FreeRTOS, Embedded Linux, UWB (FiRa, omlox, RTLS, MCTT), Devicetree/Kconfig, GCC, GDB, J-Link, PPK2, radare2, CI/CD.

Education

Développer avec le langage RUST at Cénotélie 2026 - 2026
Electronics Engineer at National University of Technology, Buenos Aires 2004 - 2013