Remote Senior Staff Engineer, Electrical Design

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Description:

  • The Senior Staff Engineer, Electrical Design will be responsible for proposing, architecting, and designing RTL in Verilog for use in a Mixed Signal Integrated Circuit.
  • They will work within a highly experienced team of engineers, contributing to clocking controls, FSM design, low power techniques, and high-speed design concepts.
  • Participation in design, architecture, and verification reviews is required.
  • The role involves covering digital backend design from synthesis, static timing, and logic equivalent checking.
  • Creating documentation targeting design, verification, and test groups is part of the responsibilities.
  • Assisting with new feature proposals, definitions, documentation, and implementation is expected.
  • Mentoring and training junior and New College Grad engineers is also a key aspect of the role.

Requirements:

  • Experience with architecting digital designs and writing device-level or sub-system specifications is necessary.
  • Proficiency in digital design implementation, logical synthesis, and DFT insertion with high coverage is required.
  • Familiarity with static timing analysis, creation of place and route constraints, formal verification, lint, and CDC/RDC checking is essential.
  • Knowledge of asynchronous clock crossings, synthesis implications of RTL, and implementing and verifying ECOs on RTL, synthesized, and post route netlists is needed.
  • Fluency in Verilog RTL coding and ASIC design methodology is a must.
  • Competence in developing design constraints for synthesis, STA, and P&R hand-off is necessary.
  • Experience with gate-level simulations, causes and implications of timing violations, ATPG generation, and ATE support is beneficial.
  • Additional experience in DFT or physical design, Verilog and/or SystemVerilog for digital design and verification is a plus.
  • Excellent oral and written communication skills are required.
  • A minimum of 8 years of direct experience in ASIC/IC design with deep knowledge of the whole IC design flow is essential.

Benefits:

  • The expected annual pay range for this position is $163,000 - $240,000, with eligibility for bonus pay.
  • Renesas offers a full range of elective benefits including medical, dental, vision, health savings account, flexible spending accounts, life insurance, AD&D, and pet insurance.
  • Benefited employees receive company-paid life insurance, AD&D, LTD, short term medical benefits, paid sick time, paid holidays, and accrued paid vacation.
  • New employees will attend a detailed benefit orientation to learn more about the many benefits and resources available.
About the job
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$ 163,000 - 240,000 USD / year
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